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mos integrated circuit m mm m pd7225 programmable lcd controller/driver data sheet document no. s14308ej6v0ds00 (6th edition) (o.d. no. ic-1555) date published june 1999 n cp (k) printed in japan ? 1986, 1999 the mark shows major revised points. the m pd7225 is a software-programmable lcd (liquid crystal display) controller/driver. the m pd7225 can be seriall y interface d wit h th e cpu in a microcomputer and can directly drive 2, 3, or 4-time division lcd. the m pd7225 contains a segment decoder which can generate specific segment patterns. i n addition , the m pd7225 can be used to control on/off (blinking) operation of a display. features ? can directly drive lcd ? programmable time-division multiplexing static drive divide-by-2, 3, or -4 time division multiplexing ? number of digits displayed 7-segment divide-by-4 time divisio n .............. . 16 digits divide-by-3 time divisio n .............. . 10 2/3 digits divide-by-2 time divisio n .............. . 8 digits stati c ................................................ . 4 digits 14-segment divide-by-4 time divisio n .............. . 8 digits ? bias m ethod static, 1/2, 1/3 ? segment decoder output 7-segmen t : numeric characters 0 to 9, six symbols 14-segmen t : 36 alphanumeric characters, 13 symbols ? blinking operation ? multi-chip configuration possible ? 8-bit serials interface 75x series and 78k series compatible ? c m o s ? single power supply ordering information part number pa ck age m pD7225G00 52-pin pla s tic qfp (14 14 mm) m pD7225G01 52-pin pla s tic qfp ( s traight) ( 14 mm) m pD7225Gb-3b7 56-pin pla s tic qfp (10 10 mm) m pD7225Gc-ab6 52-pin pla s tic qfp (14 14 mm) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet s14308ej6v0ds00 2 m m m m pd7225 pin configuration: (top view) m m m m pD7225G00 52-pin plastic qfp (14 14 mm) m m m m pD7225G01 52-pin plastic qfp (straight) ( 14 mm) m m m m pD7225Gc-ab6 52-pin plastic qfp (14 14 mm) 52 1 2 3 4 5 6 7 8 9 10 11 12 13 s19 s18 s17 s16 s15 s14 v dd s13 s12 s11 s10 s9 s8 cl1 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 nc com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 cl2 /sync v lc1 v lc2 v lc3 v ss v dd /sck si /cs /busy c, /d /reset 39 38 37 36 35 34 33 32 31 30 29 28 27 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 si : serial input cl1 : external resistor 1 (external clock) /sck : serial clock cl2 : external resistor 2 c, /d : command/data reset : reset /cs : chip select v lc1 -v lc3 : power supply for lcd drive /busy : busy v dd : power supply sync : sync v ss : ground s0-s31 : segment ic : internally connected com0-com3 : common nc : non-connection remark / indicates active low signal.
data sheet s14308ej6v0ds00 3 m m m m pd7225 m m m m pD7225Gb-3b7 56-pin plastic qfp (10 10 mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ic s7 s6 s5 s4 s3 s2 s1 s0 com3 com2 com1 com0 nc ic s19 s18 s17 s16 s15 s14 v dd s13 s12 s11 s10 s9 s8 cl2 /sync v lc1 v lc2 v lc3 v ss v dd /sck si /cs /busy c, /d /reset ic s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 cl1 ic 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 note ic pin must be connected to v dd or left unconnected.
data sheet s14308ej6v0ds00 4 m m m m pd7225 block diagram com 0 com 1 com 2 s0 com 3 s1 s29 s30 s31 display data latch data memory data pointer blinking data memory segment decoder write control command/data register serial interface command decoder /sck si v lc1 v lc2 v lc3 /sync cl1 cl2 v dd v ss /reset /cs c, /d /busy osc lcd timing control lcd driver
data sheet s14308ej6v0ds00 5 m m m m pd7225 1. pin functions 1.1 si (serial input) ?? ?? ?? ?? input this pin is used for inputting serial data (commands/data). data to be displayed as well as 19 deffernet commands for controlling the operation of the m pd7225 can be input to this pin. 1.2 /sck (serial clock) ?? ?? ?? ?? input this pin is used for inputting the shift clock for serial data (si input). the content of the si input is read into the serial register at the rising edge of this clock one bit at a time. /sck input is effective when /cs = 0 and /busy = 1. if /busy = 0, this input is ignored. if /cs = 1, this signal is ignored regardless of the /busy status. 1.3 c, /d (command/data) ?? ?? ?? ?? input this input indicates whether the signal input from the si pin is a command or data. a low level indicates data; a high level indicates a command. 1.4 /busy ?? ?? ?? ?? tri-state output this is an active-low output pin that is used to control serial data input disable/enable. a low level disables serial data input; a high level enables serial data input. this pin becomes high impedance when /cs = 1. 1.5 /cs (chip select) ?? ?? ?? ?? input when /cs is changed from high level to low level, the sck counter in the m pd7225 is cleared and serial data input is enabled. at the same time, the data pointer is initialized to address 0. when /cs is set to high level after serial data is input, the contents of the data memory are transferred to the display latch and displayed on the lcd. 1.6 /sync (synchronous) ?? ?? ?? ?? input/output the /sync pin is used to make a wired-or connection when the common pins are shared or when blinking operation is synchronized in a multi-chip configuration. when the m pd7225 is reset (/reset = 0), the /sync pin outputs the clock frequency (f cl ) divided by four (refer to figure 1-1 ), and synchronizes the system clock (f cl /4) of the m pd7225. when the reset is released (/reset =1), the display timing of each m pd7225 is synchronized with the common drive signal timing shown in figure 1-2. figure 1-1. /sync pin status during reset (/reset = 0) f cl /sync
data sheet s14308ej6v0ds00 6 m m m m pd7225 figure 1-2. /sync pin status after reset (/reset = 1) /sync com0 1 frame 1 frame 1 frame 1 frame static /sync com0 divie-by-2 time division /sync com0 divie-by-3 time division /sync com0 divie-by-4 time division 1.7 /reset ?? ?? ?? ?? input this is an active low reset input pin. 1.8 s0-s31 (segment) ?? ?? ?? ?? output these pins output segment drive signals. 1.9 com0-com3 (common) ?? ?? ?? ?? output these pins output common drive signals. 1.10 cl1, cl2 (clock) a resistor is connected across these pins for internal clock generation. when inputting an external clock, use the cl1 pin for input. 1.11 v lc1 , v lc2 , v lc3 lcd driver power supply pin.
data sheet s14308ej6v0ds00 7 m m m m pd7225 1.12 v dd positive power supply pin. either pin 7 or pin 33 can be used. 1.13 v ss gnd pin.
data sheet s14308ej6v0ds00 8 m m m m pd7225 2. internal system configuration 2.1 serial interface the serial interface consists of an 8-bit serial register and a 3-bit sck counter. the serial register clocks in the serial data from the si pin at the rising edge of /sck. at the same time, the sck counter increments (+1) the serial clock. as a result, if an overflow occurs (when eight pulses are counted), input from the si pin is disabled (/busy = 0), and the contents of the serial register is output to the command/data register. the /sck should be set to high before serial data is input and after the data has been input (after eight clocks are input to /sck). serial data must be input to the si pin beginning with msb first. msb d7 pd7225 m si pin lsb d6 d5 d4 d3 d2 d1 d0 2.2 command/data register the command/data register latches the contents of the serial register in order to process the serial data clocked into the serial register. after the serial data is latched, if the clocked in data is specified as command, the command/data register transfers its contents to the command decoder. if specified as data the command/data register transfers its contents to data memory or the segment decoder. 2.3 command decoder when the contents of the command/data register are specified as a command (c, /d was high when data was input), the command decoder, clocks in the contents of the command/data register and controls the m pd7225. 2.4 segment decoders the m pd7225 has a 7-segment decoder for use with divide-by-3 and divide-by-4 time division, and a 14-segment decoder for use divide-by-4 time division. the 7-segment decoder can generate signals for numeric characters 0 to 9 and six different symbols. the 14- segment decoder can generate signals for 36 alphanumeric characters and 13 different symbols. when the with segment decoder command is executed, if the contents of the command/data register are specified as data, the contents will be input to the segment decoder, and converted to display codes, and then automatically written to the data memory. whether to select the 7-segment decoder or 14-segment decoder is determined by the most significant bit (bit 7) of the data input to the segment decoder. it the most significant bit is 0, the 7-segment decoder will be selected. if it is 1, the 14-segment decoder will be selected. if the 7-segment decoder is selected (however, divide-by-3 and divide-by-4 time division), the lower 4 bits (bit 3 to bit 0) of the input data (c, /d = 0) will be decoded and written to the data memory. if the 14- segment decoder is selected (however, divide-by-4 time division), the lower 7 bits of the input data (c, /d = 0) will be decoded and written to the data memory.
data sheet s14308ej6v0ds00 9 m m m m pd7225 0 70 3 decode data specifies 7-segment decoder 1 70 6 decode data specifies 14-segment decoder when displaying the output of the segment decoder (display data) on the lcd, use an lcd configured as shown in figure 2-1 or figure 2-2. if another type of lcd is used, the displayed pattern will be different. figure 2-1. 7-segment type lcd when configuring the lcd for divide-by-3 time division mode, connect as follows: segn com1 com0 com2 segn + 1 segn + 2 segn segn +1 segn + 2 com0 com1 com2 : b, c, dp : a, d, g : e, f : a, b, f : c, e, g : d, dp a b c d e f dp g
data sheet s14308ej6v0ds00 10 m m m m pd7225 when configuring the lcd for divide-by-4 time division mode, connect as follows: segn com1 com0 com2 com3 segn + 1 segn segn + 1 com0 com1 com2 com3 : a, b, c, dp : d, e, f, g : a, f : b, g : c, e : d, dp a b c d e f dp g
data sheet s14308ej6v0ds00 11 m m m m pd7225 figure 2-2. 14-segment lcd the 14-segment type lcd can be used only in the divide-by-4 time division mode. for the 14-segment lcd type, connect segments and commons as follows: segn + 3 segn + 2 segn + 1 segn com3 com2 com1 com0 a d b i h g f c n m l k j e dp segn segn + 1 segn + 2 segn + 3 com0 com1 com2 com3 : h, i, k, n : d, e, f : a, b, c, dp : g, j, l, m : a, g, h : b, i, j, f : c, e, k, l : d, m, n, dp the following shows the input data and display pattern, and the configuration of the display data which is automatically written into the data memory. for the 7-segment type, the lower 4 bits (d3 to d0) are decoded. for the 14-segment type, the input data and display pattern correspond to 8-bit ascii code. the first address to which the display data is written is indicated as address n.
data sheet s14308ej6v0ds00 12 m m m m pd7225 figure 2-3. 7-segment lcd data (hex) display pattern divide-by-3 time division divide-by-4 time division data memory n n +1 n n +1 n +2 3 3 1 3 3 2 2 3 5 0 7 7 2 7 7 1 7 6 3 7 6 5 5 7 d 0 e a 3 b f 0 3 0 2 0 1 1 3 0 00 01 02 03 04 05 06 07 data (hex) display pattern divide-by-3 time division divide-by-4 time division data memory n n +1 n n +1 n +2 3 3 0 0 0 0 2 0 7 7 2 7 5 6 6 0 7 7 0 1 1 0 4 0 f b 2 f d a e 0 3 1 0 3 3 0 2 0 08 09 0a 0b 0c 0d 0e 0f
data sheet s14308ej6v0ds00 13 m m m m pd7225 figure 2-4. 14-segment lcd 0 0 0 5 f a 2 4 a display pattern data memory n+3 data (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f n+2 n+1 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 a 0 f 5 4 2 4 0 2 2 2 2 2 0 2 2 4 2 1 b display pattern data memory n+3 n+2 n+1 n 7 6 3 7 6 5 5 7 7 7 0 0 0 e 0 c 8 2 a e 0 e a 8 8 8 2 0 4 4 4 4 4 0 4 4 2 4 8 a 2 8 0 8 2 2 0 2 8 0 2 0 1 1 0 c display pattern data memory n+3 n+2 n+1 n 7 7 7 1 7 1 1 5 6 1 6 0 0 6 6 7 c 6 8 e 8 e 6 e 6 8 c 6 e 6 6 e 0 4 5 0 1 4 4 4 4 1 0 a 0 2 8 0 2 0 2 1 8 0 4 4 5 9 4 1 d display pattern data memory n+3 n+2 n+1 n 3 7 3 5 1 6 0 6 0 0 1 0 6 e 6 8 0 e 6 6 0 0 8 0 4 8 c 4 1 0 2 8 a 2 2 8 upper bit lower bits
data sheet s14308ej6v0ds00 14 m m m m pd7225 2.5 data memory/data pointer the data memory is a memory which stores display data (32 4 bits). data input by serial transfer, command immediate data, etc., is written to the data memory. specified by data pointer address 012345678910 293031 0 1 2 3 in the data memory, either data from the serial register (when the segment decoder is not used) or data from the segment decoder (when the segment decoder is used) is written as display data. when the segment decoder is not used, all bits or the lower 4 bits of the serial data (c, /d = 0) input to the serial register are assigned and written to the specific bits in location 2 to location 4 in the data memory according to the specified time division. when the segment decoder is used, the contents of the serial register (c, /d = 0) are decoded by the segment decoder, and the corresponding display data are allocated to the location specified in data memory by the time division specification (devide-by-3, -4 time division) and the msb (most significant bit) of the serial data. (1) to (4) below describe these operations. the contents of the data memory can be modified in 4-bit units or in bit units using a command. (1) static the lower 4 bits of the contents of the serial register are written to bit 0 in each address (the upper 4 bits are ignored). bit3 bit0 d3 d2 d1 d0 n + 3 n + 2 n + 1 address n only the content of bit 0 in each address are effective as display data. after the data is written, the data pointer points to address n + 4. (2) divide-by-2 time division the contents of the 4 even bits of the serial register are written to bit 0 in the four addresses, and the contents of 4 odd bits of the serial register are written to bit 1. bit3 bit0 d7 d6 d5 d4 d3 d2 d1 d0 n + 3 n + 2 n + 1 address n the contents of bits 0 and 1 of each address are effective as display data. after the data is written, the data pointer points to address n + 4. bit
data sheet s14308ej6v0ds00 15 m m m m pd7225 (3) divide-by-3 time division the contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and 2 of each address. in this case, 0 will be automatically written to bit 2 of address n + 2. for segment decoder output, 0 will also be automatically written to bit 2 (d2) of address n. bit3 bit0 0d7d6 d5d4d3 d2 0 d1 d0 n + 2 n + 1 address n the contents of bits 0, 1, and 2 of each address are effective as display data. after the data is written, the data pointer points to address n + 3. the segment decoder output written to the data memory corresponds to segments (a to g, dp) shown in figure 2-1 as follows: bit3 bit0 ef dga dpcb n + 2 n + 1 address n (4) divide-by-4 time division the contents of the 8 bits of the serial register or the segment decoder output (8 bits) are written to bits 0, 1, 2, and 3 of each address. for segment decoder output, 0 is automatically written to bit 3 (d3) of address n. bit3 bit0 d7 d6 d5 d4 d3 0 d2 d1 d0 n + 1 address n the contents of all bits of each address are effective as display data. after the data is written, the data pointer points to address n + 2. when 7 segments are used, the segment decoder output written to the data memory corresponds to segments (a to g, dp) shown in figure 2-1 as follows: bit3 bit0 deg f dpcba n + 1 address n when 14 segments are used, the segment decoder output is written to bits 0, 1, 2, and 3 of each address. in this case, 0s are automatically written to bit 3 of address n + 2, and bit 0 of address n+ 1. bit3 bit0 d15 d14 d13 d12 d11 0 d10 d9 d8 d7 d6 d5 d4 0 d3 d2 d1 d0 n + 3 n + 2 n + 1 address n
data sheet s14308ej6v0ds00 16 m m m m pd7225 all bits of each address are effective. after the data is written, the data pointer points to address n + 4. the segment decoder output written to the data memory corresponds to segments (a to n, dp) shown in figure 2-2 as follows: ml j g dpcba de f 0 nk i h n + 3 n + 2 n + 1 address n all contents of the 32 4-bit data memory are transferred to the 32 4-bit display data latch when the /cs is set to high. in this case, if the display on command has been set, the contents of the display data latch are converted to the segment drive signal in 32-bit units in synchronization with com0-com3 signals, and output from the segment pins. the figure below shows the relationship of the data memory, segment pins, and common signal selection timing. figure 2-5. data memory, segment pins, and common signal selection timing com 0 com 1 com 2 com 3 0 1 2 3 bit 012345678 address 9 10 28293031 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s28 s29 s30 s31 the data pointer (5 bits) specifies the address (0-31) of the data memory to which the display data will be written (at the same time, the data pointer specifies the blinking data memory address (0-31)). the load data pointer command is used to set the address to the data pointer (the data pointer can be initialized by setting the /cs to low). when the data pointer is counted up to 31, it then becomes 0 at the next count, and thus it repeats the operation shown below. 031 it should be noted that, if display data is written sequentially from address 0 in the divide-by-3 time division mode, addresses 30 and 31 will not be written. however, if the data is written in the divide-by-3 time division mode again, data will be written from addresses 30, 31, followed by 0 so that the display data previously written to address 0 will be modified.
data sheet s14308ej6v0ds00 17 m m m m pd7225 2.6 blinking data memory the blinking data memory stores blinking data used to control display on/off operation (blinking). blinking operation can be performed in segment units. each bit in blinking data memory corresponds to a bit in the data memory; if a bit in the blinking data memory is set to 1, the corresponding segment will blink. the blinking data memory is addressed by the data pointer at the same time the data memory is addressed. data is written by using the write blinking data memory command, and bit manipulation can be performed by using the and blinking data memory, or or blinking data memory command. the blinking on command is used to initiate blinking operation or select the blinking interval (refer to 3.2 blinking frequency setting ) 2.7 display data latch the display data latch stores the data of the 32 4-bit segment driver. each bit of the display data latch corresponds to a bit in the data memory. all contents of the data memory are transferred to the display data latch at the rising edge of /cs, and the contents displayed on the lcd are modified. if blinking is set, the contents of data memory are modified by the contents of blinking data memory and the resulting values are transferred to the display data latch. the display data written to the display data latch is successively selected by the control function performed by the lcd timing control, and converted to segment drive signal before output. 2.8 lcd driver the lcd driver consists of the segment driver and the common driver, and generates the segment drive signal and common drive signal. the segment driver outputs a segment signal so that the relationship with the common drive signal is select level if the drive data stored in the display data latch is 1. if the drive data stored in the display data latch is 0, the output of the segment driver will be non-select level. the common drive signal sequentially drives the lcd common poles according to the time divison specificaion. 2.9 lcd timing control the lcd timing control generates the lcd drive timing according to the number of time divisions, the frequency division ratio, and bias method, and supplies it to the lcd driver. in addition, the lcd timing control outputs a /sync signal from the /sync pin in order to synchronize the display timing of each m pd7225 when configured in a multi- chip configuration. in a multi-chip configuration, the common signal can be used in common or blinking operation can be synchronized by making a wired-or connection with the /sync pin of each m pd7225.
data sheet s14308ej6v0ds00 18 m m m m pd7225 3. frame frequency and blinking frequency setting 3.1 frame frequency setting the frame frequency is set according to m1, m0 (number of time-divisions setting), and f1, f0 (frequency division ratio) as indicated in the figure below. figure 3-1. frame frequency setting static divide- by-2 time division divide- by-3 time division divide- by-4 time division m1, m0 f1,f0 01111000 00 f cl 2 7 f cl 2 7 2 f cl 2 7 3 f cl 2 7 4 01 f cl 2 8 f cl 2 8 2 f cl 2 8 3 f cl 2 8 4 10 f cl 2 9 f cl 2 9 2 f cl 2 9 3 f cl 2 9 4 11 f cl 2 11 f cl 2 11 2 f cl 2 11 3 f cl 2 11 4 remark f cl = clock oscillation frequency 3.2 blinking frequency setting the blinking frequency can be set in two settings by k0 in the blinking on command. figure 3-2. blinking frequency setting k0 blinking frequency 0 f cl 2 17 1 f cl 2 16 remark f cl = clock oscillation frequency
data sheet s14308ej6v0ds00 19 m m m m pd7225 4. lcd drive power supply pin voltage setting the bias method for setting the lcd drive power supply pin allows a different voltage to be supplied to each pin. figure 4-1. voltage setting v lc1 v lc2 v lc3 static v dd v dd - v lcd v dd - v lcd 1/2 bias v dd - v lcd v dd - v lcd v dd - v lcd 1/3 bias v dd - v lcd v dd - v lcd v dd - v lcd remark v lcd : lcd voltage the following shows a circuit example which supplies voltages between vdd and vss as the lcd drive reference voltage. (1) static v lcd r 1 = r 2 v dd - v lcd v lcd : lcd drive voltage r 2 is used for contrast adjustment. (2) divide-by-2, -3 time division (1/2 bias) v lcd r 1 = r 2 2(v dd - v lcd ) 1 2 1 3 1 2 1 3 v dd v dd v lc1 v lc2 v lc3 r 1 r 2 v ss gnd pd7225 m v dd v dd v lc1 v lc2 v lc3 r 1 r 1 r 2 v ss gnd pd7225 m
data sheet s14308ej6v0ds00 20 m m m m pd7225 (3) divide-by-3, -4 time division (1/3 bias) v lcd r 1 = r 2 3(v dd - v lcd ) v dd v dd v lc1 v lc2 v lc3 r 1 r 1 r 1 r 2 v ss gnd pd7225 m
data sheet s14308ej6v0ds00 21 m m m m pd7225 5. clock circuit the clock oscillator can be configured by connecting a resistor (r) across the cl1 and cl2 clock pins. when using the external clock, cl1 can be used to input the external clock (cl2: open). figure 5-1. external circuit for clock oscillation pins osc cl1 r cl2 f cl to lcd timing control pd7225 m osc cl1 external clock open cl2 f cl to lcd timing control pd7225 m remark f cl = clock oscillation frequency (when using the external clock, this frequency is same as that of the external clock frequency.) when configuring a multi-chip system using the /sync pin, a clock with the same frequency and same phase must be supplied to the cl1 pin of each m pd7225.
data sheet s14308ej6v0ds00 22 m m m m pd7225 6. reset function when a low level of 12 clock cycles or more is input to the /reset pin, the m pd7225 will be reset to the following conditions: ? this condition is the same as when m2 - m0 = 0, f1, f0 = 0 are executed by the mode set command. ? display data transfer from the data memory to the display data latch --- this condition is the same as when the unsynchronized transfer command is executed. ? command/data register output --- this condition is the same as when the without segment decoder command is executed. ? lcd display --- this condition is the same as when the display off or the brinking off command is executed. function when the m pd7225 is reset ? s0-s31 and com0-com3 pins output v dd ? serial data input --- disabled (/busy = 0) (however, /cs = 0) when used in a multi-chip system, the reset state must be released (rising edge of /reset) within 5 m s. figure 6-1. reset signal in multi-chip system /reset 0.7v dd 0.3v dd 12 clock cycles 5 s max. m
data sheet s14308ej6v0ds00 23 m m m m pd7225 7. serial data input serial data is input to the si pin with msb first in synchronization with the serial clock in 8-bits units. when /cs is set to low, the m pd7225 sets the /busy to low (this initializes the sck counter and the data pointer to 0) in order to perform internal processing. therefore, after the m pd7225 completes internal processing, the first bit (msb) should be input in synchronization with the /sck after the /busy signal is set to high. the serial data is transferred to the serial register in bit units at the rising edge of /sck. inputting eight serial clocks completes the transfer of all 8 bits of data to the serial register. at the rising edge of the eighth serial clock, the /busy is set to low, and the status of the c, /d pin is clocked in to specify whether the data is a command or data. afterwards, the contents of the serial register are clocked into the command/data register. when successively inputting 2 or more bytes of serial data, /cs must be set to low until all bytes of data are input. the /busy is set to low each time a byte of data is input. the /busy becomes high when the serial data is clocked in from the serial register to the command/data register, so that the next serial data can be input. when input of all serial data is complete, the data memory contents can be displayed by setting /cs to high. /cs must not be set to high while display data is being transferred (before eight clocks has elapsed.) if it becomes necessary to interrupt serial data transfer when transferring two or more bytes of data due to an interrupt for the cpu interrupt, execute the pause transfer command after checking that the byte has been transferred, then set /cs to high. in this case, even if /cs is set to high, the contents of the data memory will not be transferred to the display data latch. to resume serial data transfer, set /cs to low in the same way as when initiating a normal transfer. however, in this case, the contents of the data pointer are not cleared so that data write operation starts from the next data memory address when serial data transfer is resumed (c, /d = 0). note in a multi-chip system in which the /busy pins of chips are made a wired-or connection, avoid setting the /cs pins of two or more chips simultaneously. figure 7-1. inputting byte serial data (si pin) high impedance d7 d6 d5 d0 d1 d2 high impedance /sck /cs /busy c, /d
data sheet s14308ej6v0ds00 24 m m m m pd7225 figure 7-2. inputting 5 bytes successively serial data byte 2 byte 1 byte 3 byte 4 byte 5 /cs /busy
data sheet s14308ej6v0ds00 25 m m m m pd7225 8. command 8.1 mode set 010m2m1m0f1f0 this command sets the number of time divisions for the lcd display static drive or the time-division drive, bias method, and frame frequency. (1) m1 and m0 specify the number of time divisions for static drive or time-division drive. m1 m0 0 0 ------------------- divide-by-4 time division drive 1 0 ------------------- divide-by-3 time division drive 1 1 ------------------- divide-by-2 time division drive 0 1 ------------------- static drive (2) m2 specifies the bias method. m2 0 -------------------------- 1/3 bias method 1 -------------------------- 1/2 bias method 0/1 ------------------------- static (3) f1 and f0 specify the frequency division ratio which determines the frame frequency (refer to figure 3-1). f1 f0 frequency division ratio 0 0 ------------------- 1/2 7 0 1 ------------------- 1/2 8 1 0 ------------------- 1/2 9 1 1 ------------------- 1/2 11 8.2 synchronized transfer 00110001 this command controls display data modification. normally, modification of display data is performed at the rising edge of the /cs signal (transferring display data from the data memory to the display data latch). however, after this command is executed, display data is modified at the first alternate current drive cycle (frame frequency x number of time divisions) after the /cs signal is set to high.
data sheet s14308ej6v0ds00 26 m m m m pd7225 8.3 unsynchronized transfer 00110000 this command controls display data modification. after this command is executed, display data is modified at the rising edge of the /cs pin. 8.4 pause transfer 00111000 this command disables display data modification. after this command is executed, display data can not be modified at the first rising edge of the /cs pin; instead, modification is put off until the second rising edge of the /cs pin. in addition, the data pointer is not cleared at the first rising edge of the /cs pin (refer to 2.5 data memory/data pointer ). this command is used when it becomes necessary to set the /cs pin to high due to an interrupt for the cpu in the middle of serial data input operation. 8.5 blinking on 0001101k0 this command sets the blinking operation status. the blinking frequency is set by the least significant bit of the command (bit k0). k0 blinking frequency (hz) 0f cl /2 17 1f cl /2 16 remark f cl : clock oscillation frequency 8.6 blinking off 00011000 this command stops blinking operation. 8.7 display on 00010001 after this command is executed, lcd display operation starts according to the display data contained in the display data latch.
data sheet s14308ej6v0ds00 27 m m m m pd7225 8.8 display off 00010000 when this command is executed, the relationship of all common drive signals and segment drive signals enters the non-select state. as a result, the display is turned off. transferring display data from the data memory to the display data latch is not affected by this command execution. 8.9 with segment decoder 00010101 after this command is executed, input data is sent to the segment decoder, and the decoded code is written to the data memory. 8.10 without segment decoder 00010100 after this command is executed, input data is written to the data memory without going through the segment decoder. 8.11 load data pointer 1 1 1 d4d3d2d1d0 this command sets immediate data d4-d0 to the data pointer. 8.12 write data memory 1 1 0 1 d3 d2 d1 d0 this command stores immediate data d3-d0 to the data memory addressed by the data pointer, and increments (+1) the contents of the data pointer. 8.13 or data memory 1 0 1 1 d3 d2 d1 d0 this command ors the contents of the data memory addressed by the data pointer and immediate data d3-d0, and stores the result to the data memory, then increments (+1) the contents of the data pointer.
data sheet s14308ej6v0ds00 28 m m m m pd7225 8.14 and data memory 1 0 0 1 d3 d2 d1 d0 this command ands the contents of the data memory addressed by the data pointer and immediate data d3-d0, and stores the result to the data memory, then increments (+1) the contents of the data pointer. 8.15 clear data memory 00100000 this command clears the contents of the data memory and the data pointer. 8.16 write blinking data memory 1 1 0 0 d3 d2 d1 d0 this command stores immediate data d3-d0 to the blinking data memory addressed by the data pointer, and increments (+1) the contents of the data pointer. 8.17 or blinking data memory 1 0 1 0 d3 d2 d1 d0 this command ors the contents of the blinking data memory addressed by the data pointer and immediate data d3-d0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer. 8.18 and blinking data memory 1 0 0 0 d3 d2 d1 d0 this command ands the contents of the blinking data memory addressed by the data pointer and immediate data d3-d0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer. 8.19 clear blinking data memory 00000000 this command clears the contents of the blinking data memory and the data pointer.
data sheet s14308ej6v0ds00 29 m m m m pd7225 9. display output the following describes the serial data organization, display data organization in the data memory, segment drive signal, and common drive signal when the display is active in the static and divide-by-2, -3, -4 time division modes. 9.1 static when displaying just the digit 6 in the static mode: (1) serial data organization: 0d, 07 (2) display data organization in the data memory address n + 7 n + 6 n + 5 n + 4 n +3 n + 2 n + 1 n bitcontents of bit 001111101 (3) power supply (static) v lc0 = v lc1 = v dd v lc2 = v lc3 = v dd - v lcd (4) relationship between common and segment segn + 1 segn segn + 3 segn + 6 segn + 2 segn + 5 segn + 4 com0 segn +7
data sheet s14308ej6v0ds00 30 m m m m pd7225 (5) segment and common drive signals v lc0 v lc3 segn, segn + 2 - segn + 6 v lc0 v lc3 segn + 1, segn + 7 v lc0 v lc3 com0 v lc0 0 - v lc0 0 com0 - segn com0 - segn + 1
data sheet s14308ej6v0ds00 31 m m m m pd7225 9.2 divide-by-2 time division when displaying just the digit 6 in the divide-by-2 time division mode: (1) serial data organization: f5 (2) display data organization in the data memory address n +3 n + 2 n + 1 n contents of bit 0 1 1 1 1 contents of bit 1 1 1 0 0 (3) power supply (1/2 bias) v lc0 = v dd v lc1 = v lc2 = v dd - 1/2 v lcd v lc3 = v dd - v lcd (4) relationship between common and segment segn com0 com1 segn + 3 segn + 2 segn + 1 bit
data sheet s14308ej6v0ds00 32 m m m m pd7225 (5) segment and common drive signals v lc0 v lc3 segn + 3 v lc0 v lc3 segn + 2 v lc0 v lc3 segn + 1 v lc0 v lc3 segn v lc0 v lc3 v lc1 v lc1 com0 v lc0 v lc3 com1 v lc0 0 0 - v lc0 v lc1 - v lc1 com0 - segn + 3 v lc1 - v lc1 com1 - segn t0 t1 t2 t3 t0 t1 t2 t3 t0 t1
data sheet s14308ej6v0ds00 33 m m m m pd7225 9.3 divide-by-3 time division when displaying the digit 6. in the divide-by-3 time division mode: (1) serial data organization ? without segment decoder: fe ? with segment decoder : 06 (however, the floating point is set to 1 by command.) (2) display data organization in the data memory address n + 2 n + 1 n contents of bit 0 1 1 0 bit contents of bit 1 1 1 1 contents of bit 2 0 1 1 (3) power supply (1/3 bias) v lc0 = v dd v lc1 = v dd - 1/3 v lcd v lc2 = v dd - 2/3 v lcd v lc3 = v dd - v lcd (4) relationship between common and segment segn + 1 com2 segn com1 segn + 2 com0
data sheet s14308ej6v0ds00 34 m m m m pd7225 (5) segment and common drive signals v lc0 v lc3 segn + 1 v lc0 v lc1 v lc2 v lc1 v lc2 v lc1 v lc2 v lc1 v lc2 v lc1 v lc2 v lc1 v lc2 v lc3 segn v lc0 v lc3 segn + 2 v lc0 v lc3 com0 v lc0 v lc3 com1 v lc0 v lc0 com2 v lc0 0 0 - v lc0 v lc2 - v lc2 com1 - segn + 2 v lc2 - v lc2 com2 - segn + 2 t0 t1 t2 t3 t4 t5 t0 t1 t2 t3
data sheet s14308ej6v0ds00 35 m m m m pd7225 9.4 divide-by-4 time division when displaying the digit 6. in the divide-by-4 time division mode: (1) serial data organization ? without segment decoder: fd ? with segment decoder : 06 (however, the floating point is set to 1 by command.) address n + 1 n contents of bit 0 1 1 contents of bit 1 1 0 contents of bit 2 1 1 contents of bit 3 1 1 (2) power supply (1/3 bias) v lc0 = v dd v lc1 = v dd - 1/3 v lcd v lc2 = v dd - 2/3 v lcd v lc3 = v dd - v lcd (3) relationship between common and segment segn segn + 1 com1 com3 com0 com2 bit
data sheet s14308ej6v0ds00 36 m m m m pd7225 (4) segment and common drive signals v lc0 t7 t0 t1 t2 t7 t0 t1 t2 t3 t4 t5 t6 v lc1 v lc2 v lc3 segn + 1 v lc0 v lc1 v lc2 v lc3 segn v lc0 v lc1 v lc2 v lc3 com0 v lc0 v lc1 v lc2 v lc3 com3 v lc0 v lc1 v lc2 v lc3 com1 v lc0 v lc1 v lc2 v lc3 com2 v lc0 v lc2 0 - v lc2 - v lc0 com0 - segn + 1 v lc2 0 - v lc2 com1 - segn
data sheet s14308ej6v0ds00 37 m m m m pd7225 10. electrical characteristics absolute maximum rating (t a = 25 c) item symbol condition rating units power supply voltage v dd - 0.3 to +7.0 v input voltage v i - 0.3 to v dd +0.3 v output voltage v o - 0.3 to v dd +0.3 v operating ambient temperature t a - 10 to +70 c storage temperature t stg - 65 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. capacitance (t a = 25 c, v dd = 0 v) item symbol condition min. typ. max. units input capacitance c in 10 pf output capacitance c out1 except /busy 20 pf output capacitance c out2 /busy 15 pf input/output capacitance c io /sync 15 pf clock capacitance c c cl1 30 pf f = 1 mhz pins other than those used for measurement are 0 v.
data sheet s14308ej6v0ds00 38 m m m m pd7225 dc characteristics (t a = - - - - 10 to +70 c, v dd = 5 v 10%) item symbol condition min. typ. max. unit high level input voltage v ih 0.7 v dd v dd v low level input voltage v il 0 0.3 v dd v high level output voltage v oh /sync, /busy, i oh = - 10 m av dd - 0.5 v low level output voltage v ol1 /busy, i ol = 100 m a0.5v v ol2 /sync, i ol = 900 m a1.0v output short-circuit current i os /sync, v o = 1 v - 300 m a high level input leakage current i lih v i = v dd 2 m a low level input leakage current i lil v i = 0 v - 2 m a high level output leakage current i loh v o = v dd 2 m a low level output leakage current i lol v o = 0 v - 2 m a common output impedance r com com0 to com3 note 1 , v dd 3 v lcd 57k w segment output impedance r seg s0 to s31 note 1 , v dd 3 v lcd 714k w power supply voltage i dd cl1 external clock, f c = 200 khz note 2 100 250 m a notes 1. applies to static, 1/2 bias, 1/3 bias 2. abnormal current will flow if the external clock supply is removed. dc characteristics (t a = 0 to +70 c, v dd = 2.7 to 5.5 v) item symbol condition min. typ. max. units high level input voltage v ih1 except /sck 0.7 v dd v dd v v ih2 /sck 0.8 v dd v dd v low level input voltage v il1 except /sck 0 0.3 v dd v v il2 /sck 0 0.2 v dd v high level output voltage v oh /sync, /busy, i oh = - 7 m av dd - 0.75 v low level output voltage v ol1 /busy, i ol = 100 m a0.5v v ol2 /sync, i ol = 400 m a0.5v output short-circuit current i os /sync, v o = 0.5 v - 200 m a high level input leakage current i lih v i = v dd 2 m a low level input leakage current i lil v i = 0 v - 2 m a high level output leakage current i loh v o = v dd 2 m a low level output leakage current i lol v o = 0 v - 2 m a common output impedance r com com0 to com3 note 1 , v dd 3 v lcd 6k w segment output impedance r seg s0 to s31 note 1 , v dd 3 v lcd 12 k w power supply voltage i dd cl external clock, v dd = 3 v 10%, f c = 140 khz note 2 30 100 m a notes 1. applies to static and 1/3 bias 2. abnormal current will flow if the external clock supply is removed.
data sheet s14308ej6v0ds00 39 m m m m pd7225 ac characteristics (t a = - - - - 10 to +70 c, v dd = 5 v 10%) item symbol condition min. typ. max. units operating frequency f c 50 200 khz oscillation frequency f osc r = 180 k w 5% 85 130 175 khz high level clock pulse width t whc cl1, external clock 2 16 m s low level clock pulse width t wlc cl1, external clock 2 16 m s /sck frequency t cyk 900 ns high level /sck pulse width t whk 400 ns low level /sck pulse width t wlk 400 ns /busy -? /sck hold time t hbk 0ns si set time (against /sck - )t sik 100 ns si hold time (against /sck - )t hki 200 ns 8th pulse of /sck -? /busy delay time t dkb c l = 50 pf 3 m s /cs ? /busy delay time t dcsb c l = 50 pf 1.5 m s /busy low level time t wlb t whcs 3 48/f c note 1 c l = 50 pf 4 44 (57) note 2 1/f c c, /d set time (against 8th pulse of sck - ) t sdk 9 m s c, /d hold time (against 8th pulse of sck - ) t hkd 1 m s /cs hold time (against 8th pulse of sck - ) t hkcs 1 m s high level /cs pulse width t whcs note 3 m s low level /cs pulse width t wlcs note 3 m s /sync load capacitance c lsy t cyc = 5 m s50pf notes 1. unsynchronized transfer mode for synchronized transfer mode, t whcs 3 (48/f c + ac driver frequency) 2. blinking on 3. 8/fc
data sheet s14308ej6v0ds00 40 m m m m pd7225 ac characteristics (t a = 0 to +70 c, v dd = 2.7 v to 5.5 v) item symbol condition min. typ. max. unit operating frequency f c 50 140 khz oscillation frequency f osc r = 180 k w 5%, v dd = 3 v 10 % 50 100 140 khz high level clock pulse width t whc cl1, external clock 3 16 m s low level clock pulse width t wlc cl1, external clock 3 16 m s /sck frequency t cyk 4 m s high level /sck pulse width t whk 1.8 m s low level /sck pulse width t wlk 1.8 m s /busy -? /sck hold time t hbk 0ns si set time (against /sck - )t sik 1 m s si hold time (against /sck - )t hki 1 m s 8th pulse of /sck -? /busy delay time t dkb c l = 50 pf 5 m s /cs ? /busy delay time t dcsb c l = 50 pf 5 m s /busy low level time t wlb t whcs 3 48/f c note 1 c l = 50 pf 4 44 (57) note 2 1/f c c, /d set time (against 8th pulse of sck - ) t sdk 18 m s c, /d hold time (against 8th pulse of sck - ) t hkd 1 m s /cs hold time (against 8th pulse of sck - ) t hkcs 1 m s high level /cs pulse width t whcs note 3 m s low level /cs pulse width t wlcs note 3 m s /sync load capacitance c lsy t cyc = 7.1 m s50pf notes 1. unsynchronized transfer mod for synchronized transfer mode, t whcs 3 (48/f c + ac driver frequency) 2. blinking on 3. 8/fc ac timing measurement voltage measurement points 0.7v dd 0.3v dd 0.7v dd 0.3v dd
data sheet s14308ej6v0ds00 41 m m m m pd7225 timing wave-form cl1 /cs /busy /sck si c, /d t cyc (1/fe) t whc t wlc t wlcs t hbk 0.5 v 0.5 v t cyk t wlk t whk t sik t hki t sdk t hkd t dkb t wlr t dcsb note 1 note 2 note 3 t whcs t hkcs notes 1. v dd - 0.5 v when v dd = 5 v 10 %, v dd - 0.75 v when v dd = 2.7 to 5.5 v 2. 0.8 v when v dd = 2.7 v to 5.5 v 3. 0.2 v when v dd = 2.7 v to 5.5 v
data sheet s14308ej6v0ds00 42 m m m m pd7225 typical characteristic curve (t a = 25 c) external resistor and oscillation frequency external resistor r (k ohms) oscillation frequency (khz) 200 50 100 200 500 100 cl2 cl1 r power supply voltage and operating current power supply voltage vdd (v) operating current ( a) 4 20 50 100 56 3 cl2 cl1 external clock power supply voltage and oscillation frequency power supply voltage vdd (v) oscillation frequency (khz) 45 80 100 120 140 6 3 cl2 cl1 r f c = 200 khz f c = 140 khz v dd = 3 v v dd = 5 v r = 180 k w m
data sheet s14308ej6v0ds00 43 m m m m pd7225 11. package drawings m m m m pD7225G00 m s 52 pin plastic qfp (14x14) notes 1. controlling dimension millimeter. 2. each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. i item millimeters inches b 14.0 0.2 0.551 d 21.0 0.4 0.827 0.016 f 1.0 0.039 a 21.0 0.4 0.827 0.016 h 0.42 0.08 0.017 i 0.20 0.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. p52g-100-00-3 + 0.009 - 0.008 + 0.003 - 0.004 g 1.0 0.039 j 1.0 (t.p.) 0.039 k 3.5 0.2 0.138 + 0.008 - 0.009 l 2.2 0.2 0.087 + 0.008 - 0.009 detail of lead end q k l p h g f s j n c 14.0 0.2 0.551 + 0.009 - 0.008 m 0.17 0.007 + 0.003 - 0.004 + 0.08 - 0.07 n 0.15 0.006 p 2.6 0.102 + 0.009 - 0.004 + 0.2 - 0.1 39 40 26 27 1 52 14 13 s a b cd m
data sheet s14308ej6v0ds00 44 m m m m pd7225 m m m m pD7225G01 52pin plastic qfp (straight) ( 14) item millimeters inches note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. p52g-100-01-2 a c d b d 22.00.4 0.8660.016 f 1.0 0.039 g 1.0 0.039 f g i p k m u t b 14.00.2 0.551 +0.009 C0.008 c 14.00.2 0.551 +0.009 C0.008 h 0.400.10 0.016 +0.004 C0.005 p 2.6 0.102 +0.009 C0.004 t 1.0 0.039 u 1.45 0.057 m h j a 22.00.4 0.8660.016 i 0.20 0.008 j 1.0 (t.p.) 0.039 (t.p.) k 4.00.2 0.157 +0.009 C0.008 m 0.15 0.006 +0.004 C0.003 +0.10 C0.05 +0.2 C0.1 39 40 52 1 14 13 27 26
data sheet s14308ej6v0ds00 45 m m m m pd7225 m m m m pD7225Gb-3b7 56 pin plastic qfp (10 10) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. s56gb-65-3b7-3 r5 ? 5 ? 5 ? 5 ? s 3.0 max. 0.119 max. n detail of lead end i j f g h q r p k m l a 13.20.4 0.5200.016 b 10.00.2 0.3940.008 c 10.00.2 0.3940.008 d 13.20.4 0.5200.016 f 0.75 0.030 g 0.75 0.030 l 0.80.2 0.031 +0.009 C0.008 h 0.300.10 0.012 +0.004 C0.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60.2 0.0630.008 m 0.15 0.006 +0.004 C0.003 n 0.10 0.004 p 2.7 0.106 q 0.10.1 0.0040.004 +0.10 C0.05 m 39 40 27 26 14 13 1 52 a b cd s
data sheet s14308ej6v0ds00 46 m m m m pd7225 m m m m pD7225Gc-ab6 52 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. p52gc-100-ab6-4 l 0.8 0.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.6 0.102 a 17.6 0.4 0.693 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f 1.0 0.039 g 1.0 0.039 h 0.40 0.10 0.016 +0.004 ?.005 i 0.20 0.008 j 1.0 (t.p.) 0.039 (t.p.) k 1.8 0.2 0.071 +0.008 ?.009 q 0.1 0.1 0.004 0.004 +0.10 ?.05 +0.004 ?.003 m m k j h q p n r detail of lead end i g r5 5 5 5 s 3.0 max. 0.119 max. 39 40 52 1 26 27 14 13 a b cd l f s
data sheet s14308ej6v0ds00 47 m m m m pd7225 12. recommended soldering conditions when mounting the m pd7225 by soldering, soldering should be performed under the following recommended conditions. should other than recommended conditions be used, consult with our sales personnel. surface mount type m pD7225G00 : 52-pin plastic qfp (14 14 mm) m pD7225G01 : 52-pin plastic qfp (straight) ( 14 mm) m pD7225Gc-ab6 : 52-pin plastic qfp (14 14 mm) soldering method soldering condition symbol of recommended soldering condition partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) - m pD7225Gb-3b7 : 56-pin plastic qfp (10 10 mm) soldering method soldering condition symbol of recommended soldering condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: 3 max. ir35-00-3 vps package peak temperature: 215 c, time: 40 seconds max. (200 c min), number of times: 3 max. vp-15-00-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., number of times: 1, preheating temperature: 120 c max. (package surface) ws-60-00-1 caution do not use two or more soldering methods in combination (except the partial heating method). reference documents nec semiconductor device reliability / quality control system (c10983e) quality grades to necs semiconductor devices (c11531e) semiconductor device mounting technology manual (c10535e)
data sheet s14308ej6v0ds00 48 m m m m pd7225 [memo]
data sheet s14308ej6v0ds00 49 m m m m pd7225 [memo]
data sheet s14308ej6v0ds00 50 m m m m pd7225 [memo]
data sheet s14308ej6v0ds00 51 m m m m pd7225 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd7225 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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